(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to the filling of trench lines and via holes simultaneously in a dual damascene structure utilizing selective-W CVD process.
(2) Description of the Related Art
Dual damascene process is used more and more in the manufacturing of semiconductor devices because the process makes it possible to form interconnect lines and vias simultaneously, thus eliminating several conventional steps of forming them separately in a serial fashion. However, the characteristics of the vias and trench lines are usually degraded unless certain process steps are developed to take advantage of the damascene process while restoring the integrity of the integrated structure. The disclosed dual damascene process using selective-tungsten (W) chemical vapor deposited (CVD) tungsten (W) provides a relatively simple method of achieving the desired integrity for both the vias and the interconnect lines in a dual damascene structure.
The damascene process itself is a technique where metal interconnections are inlaid in performed grooves in a substrate, and is usually a preferred method of fabricating interconnections for integrated circuits. In contrast, the more conventional interconnections are formed by blanket depositing a conductive material on an insulation layer such as silicon oxide, and then etching the desired wiring pattern on the layer. The vertical connections between the wiring layers are made separately by forming holes in the insulation layers separating the metallized layers and then filling them with the same or a different conductive material.
Normally, a semiconductor substrate contains passive and active regions having active devices formed near the surface of the semiconductor substrate. The active devices are interconnected through an interlevel conductive layer. One or more metal wiring layers are then formed overlying the interlevel dielectric layer and are separated from each other by additional insulating layers. The wiring stripes are connected to each other and to the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist mask formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes, or windows, that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required "personalized" wiring layer.
The more advanced process of forming interconnects with dual damascene is illustrated in FIGS. 1a-1d where, in addition to forming the grooves of single damascene, conductive via openings are also formed. In FIG. 1a of prior art, two layers of insulating layer, that is, lower layer (30) and upper layer, (40), are shown deposited on a first level interconnect metal layer (25) already formed on substrate (10). There is usually an etch stop layer between layers (30) and (40), depicted as reference to numeral (43).
In this conventional dual damascene process, then, insulating layer (30) is coated with a photoresist (not shown) which is exposed through a first mask with image pattern of the via openings (35) and the pattern is anisotropically etched in upper insulating layer (40), that is, down to the etch stop layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the opening for the conductive ones in the upper insulating layer, the via openings (35) already present in the upper insulating layer are simultaneously etched and replicated in the lower layer of insulating material (30). After the etching is complete, both the vias, (35), and line openings, or trenches, (45), are filled with metal (50) as shown in FIG. 1c. Finally, the substrate is subjected to chemical mechanical polishing until the underlying insulating material (40) is reached and the substrate surface, which is now inlaid with metal (55), is planarized for further processing.
Dual damascene is an improvement over single damascene because it permits the filling of both the trenches and the vias with metal at the same time, thereby eliminating process steps. Although this conventional damascene offers advantages over other processes for forming interconnections, it has a number of shortcomings, such as forming and filling the vias. For example, the edges of via openings in the lower insulating layer, after the second etching, are poorly defined because of the two etchings. In addition, because of the manner of filling the vias with metal voids (FIG. 2a) or key holes (FIG. 2b) are formed within the voids, resulting in reliability and via resistance problems.
In conventional via filling, as in most applications when contact holes and vias are less than 1.5 micrometers (.mu.m), sloped vias are necessary to ensure adequate coverage (sometimes referred to as step-coverage) of the opening, or the mouth, of the via, with metal. This is because, as it is known in the art, when physical vapor deposition is used to deposit metal over holes, straight sidewalls result in worse step-coverage by the metal than if the sidewalls are sloped. On the other hand, the competing ultra-scale integration (ULSI) integrated circuit technology is demanding that the holes be formed ever so closely together, thus forcing the sloped walls to be vertical and straight. Then, with vertical walls, the aspect ratio (depth over width) dependence of the step coverage into contact holes and vias become critical as feature size are scaled into the submicron regime. It is found, for example, that as the aspect ratio increases to 1.0 so that the hole depth equals the width, the metal coverage over the edges of the hole is less than 5%. (See, S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 241.)
Among metals suitable for via and contact hole filling, tungsten, W, has been found to give the best conformal coverage of the topography of holes. There are generally two methods that have been developed for filling holes, and they are, blanket CVD W and etchback, and selective CVD W. Blanket chemical vapor deposition of tungsten is accomplished using silane reduction. However, as the deposition proceeds, the sidewalls of the vias are covered by the conformal CVD W film and they eventually become thick enough that they come into contact with one another. In the ideal case, the holes are thereby filled. In practice, however, keyholes, such as shown in FIG. 2b form. Furthermore, it is found that the density of the tungsten plug formed in the via hole is low. Similar problems also do occur with selective-W CVD as well.
Some of the problems cited above are addressed by workers in the field. Hwang, et al., in U.S. Pat. No. 5,661,080 disclose a method for fabricating a tungsten plug in a contact hole by depositing a tungsten film of a predetermined thickness several times to form a multilayer structure, thereby increasing the density of the tungsten plug. This is accomplished by forming a contact hole, forming a glue layer over the entire exposed surface of the resulting structure including the contact hole and the exposed surface of the insulating film, depositing a blanket tungsten films to a small thickness over the glue layer, depositing a seed layer to a small thickness over the blanket tungsten film, sequentially depositing another blanket tungsten film and another seed layer over the seed layer and repeating the sequential deposition. In another U.S. Pat. No. 5,462,890 by Hwang, et al., a similar method of making a tungsten plug is shown without the key-holes.
A dual damascene structure is described by Chang, et al., in an article in "ULSI Technology" published by the McGraw-Hill Company, Inc., 1997, pp.444-445. A self-aligned via dual damascene process is also described by Avanzino in U.S. Pat. No. 5,614,765, while method of making dual damascene antifuse structure is disclosed in U.S. Pat. No. 5,602,053.
However, the present invention is different from prior art in that a seeded selective W CVD is disclosed which restores full integrity to tungsten plugs as described fully in the embodiments of the instant invention.